(1) Field of the Invention
The present invention relates to solid state imaging devices each including an imaging region which has a plurality of pixels over a semiconductor substrate, methods for fabricating the same, and cameras.
(2) Description of Related Art
A MOS (Metal Oxide Semiconductor) solid state imaging device is an image sensor in which a signal accumulated in a photodiode forming a corresponding pixel is read by an amplification circuit including a MOS transistor. Such a MOS solid state imaging device is advantageously capable of low voltage operation and high-speed charge reading and can be integrated with peripheral circuits into one chip.
In view of the above, attention has been paid to MOS solid state imaging devices as imaging devices used for digital cameras and portable devices, such as mobile phones. In recent years, particularly, for the MOS solid state imaging devices, reduction in cell size and improvement in sensitivity have been especially demanded.
An imaging region of a typical MOS solid state imaging device is formed of a photodiode formed in a silicon substrate, a floating diffusion, a MOS transistor, and a device isolation region for electrically isolating these elements from one another. Generally, an STI (shallow trench isolation) region is formed as the device isolation region.
The device isolation region is formed by STI in the following manner: In order to satisfy the isolation characteristics, a trench is formed in the top surface of the silicon substrate by etching, and then the trench is filled with an oxide film. In this etching, the amount of unnecessary electric charges produced even under dark conditions on which the silicon substrate is not irradiated with light increases due to etching damage, resulting in a deterioration in noise characteristics. Furthermore, to cope with the reduction in cell size, the STI structure prevents the photodiode from laterally spreading out. This decreases the number of electrons accumulable in the photodiode.
In order to solve the above-mentioned problems occurring when the isolation region is formed by STI, a solid state imaging device according to a known example which will be described below has been suggested.
FIG. 7 illustrates a cross-sectional structure of a part of a solid state imaging device including a photodiode according to the known example (for example, Japanese Unexamined Patent Application Publication No. 2005-191262).
As illustrates in FIG. 7, a P-type buried region 104 is formed in the top surface of an N-type charge accumulation region 103 formed in the top surface of a P-type semiconductor well region 102 of a semiconductor substrate 101. A trench formed in the semiconductor substrate 101 is filled with a device isolation layer 111 made of an insulating layer. The device isolation layer 111 is adjacent to a photodiode and composed of a wide upper part 109 and a narrow lower part 110. A P-type region 112 is formed to surround the narrow lower part 110. In addition to these elements, the following elements are illustrated in this figure: a floating diffusion 105; a gate insulating film 106; a read-out gate electrode 107, a reset gate electrode 108; a gate electrode 113; via interconnects 114; and metal interconnects 115.
According to the solid state imaging device illustrated in FIG. 7, the photodiode is electrically isolated from other peripheral elements in the top surface of the semiconductor substrate 101, and the width of the device isolation region can be reduced. Therefore, even when the pixel size is reduced, the amount of the accumulable charges can be sufficiently secured.
However, the solid state imaging device of the known example has problems that will be described below.
In the solid state imaging device of the known example illustrated in FIG. 7, the P-type region 112 is formed to surround the lower part 110 forming part of the device isolation layer 111 and is not connected to the P-type buried region 104. Dark current produced at the interface of the device isolation layer 111 is collected on part of the bottom surface of the upper part 109 forming part of the device isolation layer 111, i.e., at the boundary of the P-type buried region 104 and the P-type region 112, resulting in a deterioration in characteristics. Furthermore, additional dark current is produced at the upper edge of the upper part 109 forming part of the device isolation layer 111, because stresses are concentrated thereat and the upper edge are not covered with the P-type region 112. Moreover, in order to form the isolation layer 111, a lithography method and a dry etching method are used to form the upper part 109 of the device isolation layer 111, and these methods are again used to form the lower part 110 of the device isolation layer 111. For this reason, the location at which the lower part 110 is formed may become misaligned due to variations in the dimensions of a resist pattern used for the lithography method and mask misalignment. This causes the dimensions and location of the lower part 110 forming part of the device isolation layer 111 to vary from pixel to pixel and from wafer to wafer. As a result, performance variations in the number of the accumulable electrons and sensitivity are caused. This prevents a high-performance solid state imaging device from being achieved. Furthermore, since lithography needs to be carried out twice, the TAT (turn around time) is increased, resulting in increased cost.